(Section 2.

(Section 2.1.4) Some authors have advocated that the target address calculation for a branch and the register comparison be both done in the ID stage, arguing that the comparison can be done very fast (e.g., at the same time as the source registers are copied in the ID/EX register).(a) What changes are to be made to the forwarding unit and the stalling control unit in order to implement this optimization?(b) How many cycles will be saved if both registers are available?

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